1. Field of the Invention
The present invention relates to a clock-based data storage device, and more particularly to a clock-based data storage device, a dual pulse generation device, and a data storage device, which can reduce internal capacitance and improve loading at an output port so that a switching speed increases, and electric power consumption is reduced and is more effectively used.
2. Description of the Prior Art
FIG. 1 is a circuit diagrams of a Hybrid Latch Flip Flop (hereinafter, referred to as “HLFF”). With reference to FIG. 1, an HLFF includes a dynamic front port and a static back port. When a clock signal Ck shifts from a high level to a lower level in the HLFF as shown in FIG, 1, input data is transmitted to the front port during delay time of an inverted/delayed clock signal CkDB inverted and delayed by three inverters, a charged or, discharged state or a previous state of the front port is kept, and a prior logic state (pull-up or pull-down) of the back port is kept as it is. When the level of a clock signal Ck shifts from a low level to a high level, the front port dose not receive input data D any more, and the back port transmits the previous logic port to the back port so as to output it.
FIG. 2 is a circuit diagram of a conventional Semi-Dynamic Flip Flop (hereinafter, referred to as “SDFF”). With reference to FIG. 2, the SDFF includes a precharge port and an output buffer port. In the SDFF as shown in FIG 2, when input data D is in a logic high state, the precharge port is completely discharged so that output Q becomes a logic high state (pull-up), and when input data D is in a logic low state, the precharge port is charged to be a logic high state so that ouput Q becomes a logic low state (pull-down).
As shown in FIGS. 1 and 2, the conventional HLFF and SDFF as described above include one dynamic node X so that the one dynamic node X is connected with an output transistor p-channel as well as an output transistor N-channel, thereby generating large internal capacitance which always generates regardless of a pull-up and pull-down shift. Accordingly, in the conventional Flip Flop, a switching speed decreases due to the internal large capacitance, which is always generated, power leakage occurs, and an operational speed decreases due to a discharging path in a stack structure of a transistor disposed at an output port.